Television with integrated receiver decoder

ABSTRACT

A television set includes an integrated receiver decoder. By integrating the receiver/decoder with the television, some circuitry and memory are shared. Moreover, a digital video signal provided by the receiver/decoder need not be converted to an analog NTSC signal before transmission to the television CRT. In one embodiment, where a television having a 16×9 aspect ratio is used, on-screen display data is displayed without distortion.

FIELD OF THE INVENTION

The present invention relates generally to television receivers and,more particularly, to those television receivers having shared circuitrywith digital receiver/decoders.

BACKGROUND

Despite the proliferation of digital computer systems in the homeenvironment, most audio/video components, especially televisionreceivers, remain analog oriented. As a result, devices such as videocassette recorders (VCR), digital video disk (DVD) players and digitalsatellite system (DSS) integrated receiver decoders (IRDs) must providean analog output signal to a television receiver. In general, thisanalog output signal will be formatted to the NTSC standard for theUnited States.

For example, a typical DSS IRD is shown in FIG. 1. Digital signals froman orbiting satellite are received at antenna 110 attached to the IRDfront-end 1. The digital signals are typical encrypted MPEG streamscontaining television programming as well as audio-only programming. TheIRD front-end 1 is a tuner which allows a user to select a desiredchannel. The front-end 1 also provides amplification of the relativelyweak signal received at antenna 110. For the case where a user wishes toview television programming provided by the digital satellite systemservice provider, switch 33 will couple the selected channel signal fromfront-end 1 to the transport parser (TPP) 2. In some cases, the DSS IRDwill be connected to other elements of a home entertainment systemthough an interface (I/F) which may comply with the IEEE standardsdocument 1394 entitled Standard for High Performance Serial Bus(hereafter, the "IEEE 1394 Serial Bus Standard"). The 1394 I/F 3 mayconnect the DSS IRD to a variety of video cassette recorders, digitalvideo disk players, and other audio/visual or computer components. Whenthe user wishes to use the DSS IRD as a home entertainment systemcommand unit, digital signals from these other components can besupplied though 1394 I/F 3 across a corresponding serial bus. In thosecases, switch 33 will be oriented so as to connect TPP 2 to 1394 I/F 3.

Transport parser 2 also includes a data encryption standard (DES) block.TPP/DES 2 parses and decrypts the digital bit stream received fromfront-end 1 (typically, signals received from 1394 I/F 3 will already bedecrypted and will bypass the decryption engine in TPP/DES 2). Thedecrypted bit stream is then passed though traffic controller (TC) 4 andis stored in RAM 5. RAM 5 may be a 16 megabyte synchronous dynamic RAMfor one embodiment. For those cases where a user wishes to recordsignals received from the digital satellite system service, thedecrypted bit stream from TPP/DES 2 is also transmitted to otheraudio/visual components, for example a digital video cassette recorder,though 1394 I/F 3.

Traffic controller 4 distributes the stored data from RAM 5 to anappropriate decoder. This may be either video decoder 7 or audio decoder8. For the case of video data, the signal is passed from RAM 5 thoughtraffic controller 4 to video decoder (VDEC) 7 where it is decodedaccording to the MPEG standards. Likewise, audio data is transferredfrom RAM 5 though traffic controller 4 to audio decoder (ADEC) 8 fordecoding. Up to this point, both the audio and video signals are indigital format. However, these signals must be converted to an analogformat for presentation through a conventional television set.Accordingly, audio signals are converted in digital-to-analog (D/A)converter 13 before being passed to a speaker. Video signals areconverted from a digital to an analog signal and the analog signal isencoded according to the NTSC standard in NTSC encoder 12. This NTSCsignal may be transmitted to an analog video cassette recorder.

In addition, video signals must be passed from video decoder 7 to theanalog television set. Accordingly, a second NTSC encoder 100 isprovided for this purpose. The video signals may be mixed in mixer 9with on screen display data, such as a programming table, before beingencoded. The on screen display data present in the MPEG stream isdecoded by on screen display block 6 prior to mixing.

All of the above operations are controlled via control signals providedby central processing unit 15.

Because the digital video signal must be converted to an analog NTSCsignal for transmission to the television set, picture quality isdegraded. Accordingly, it would be desirable to have a means fordecrypting and decoding digital television broadcast signals withouthaving to convert such digital signals to analog NTSC signals beforepresentation.

SUMMARY OF THE INVENTION

The present invention provides a television set with an integrateddigital receiver/decoder. By integrating the receiver/decoder with thetelevision, some circuitry and memory can be shared. Moreover, thedigital video signal provided by the receiver/decoder need not beconverted to an analog NTSC signal before transmission to thetelevision. Accordingly, picture quality is less degraded than insystems utilizing standard NTSC connections. In one embodiment, where atelevision having a 16×9 aspect ratio is used, on screen display data isdisplayed without distortion.

In one embodiment, a television has first circuitry for decoding anddisplaying television signals having a first format, e.g., NTSC signals.The television also has second circuitry for decoding and displayingtelevision signals having a second format, e.g., MPEG signals. The firstand second circuitry are coupled together and may include a sharedmemory. The first circuitry may include circuitry for separatingluminance and chrominance information and circuitry for using suchinformation to generate RGB signals for display. The second circuitrymay include MPEG decoders for video and audio data.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and notlimitation in the figures of the accompanying drawings in which likenumerals indicate similar elements and in which:

FIG. 1 illustrates an exemplary digital satellite system integratedreceiver decoder which provides an analog output;

FIG. 2 illustrates one embodiment of a television having an integratedreceiver decoder according to the present invention;

FIG. 3 illustrates a second embodiment of a television with anintegrated receiver decoder according to the present invention;

FIGS. 4 illustrates a digital process in which luminance information isseparated from chrominance information;

FIG. 5 illustrates luminance/chrominance separators for the televisionshown in FIG. 2;.

FIG. 6 is a memory map for a random access memory of a television havingan integrated receiver decoder;

FIG. 7 illustrates a non-interlace converter for use with a televisionhaving an integrated receiver/decoder; and

FIG. 8 illustrates a mixed television signal containing video data andon screen display data.

DETAILED DESCRIPTION

A television with an integrated receiver decoder is disclosed. Althoughthe present invention is described with reference to a digital satellitesystem integrated receiver decoder (DSS IRD), those skilled in the artwill appreciate that the present invention is also applicable to theintegration of any digital audio/video component capable of decodingMPEG streams with a television receiver. FIG. 2 illustrates oneembodiment of a digital television set with an integratedreceiver/decoder.

As was the case for the conventional DSS IRD shown in FIG. 1, in theintegrated system of FIG. 2 antenna 110 receives digital signalsprovided by a digital satellite system service provider and outputsthose signals to a tuner/front-end 1. Tuner/front-end 1 allows a user toselect a desired channel and also amplifies the relatively weak signalprovided by antenna 110. For the case where a user wishes to view DSSprogramming, switch 33 is oriented so as to connect tuner/front-end 1 toTPP/DES block 2.

The DSS IRD portion of the integrated system also provides an Interface3 to connect to other digital audio/visual components. Interface 3preferably operates according to the IEEE 1394 Serial Bus Standard, asdescribed above. In other embodiments, however, other digital networksmay be used and Interface 3 will operate accordingly. For the case wherethe user wishes to view pre-recorded programming, switch 33 is orientedso as to connect Interface 3 to the TPP/DES block 2.

The digital signal is parsed and decrypted (if necessary) by TPP/DESblock 2 and passed to traffic controller 4. Traffic controller 4 storesthe decrypted bit stream in RAM 5, which may be a 16 megabytesynchronous dynamic RAM. For the case where a user wishes to record theprogramming, the decrypted bit stream is also transmitted to otheraudio/visual components across the 1394 serial bus though Interface 3.

Traffic controller 4 distributes the stored data in RAM 5 to videodecoder 7 and audio decoder 8 as appropriate. Video decoder (VDEC) 7receives video data from RAM 5 and decodes it according to the MPEGstandard. Similarly, audio decoder 8 receives audio data from RAM 5 anddecodes it according to the MPEG standard. The decoded audio signal ispassed from audio decoder 8 to digital-to-analog converter 13 where itis converted to an analog signal. This analog audio signal is thenpassed to a speaker system. Switch 14 connects the digital-to-analogconverter 13 to the speaker system when the integrated system is in areceiver/decoder mode. In a television mode, switch 14 will connect thespeaker system to an audio detector/amplifier 19.

On screen display data stored in RAM 5 as part of the MPEG stream istransmitted though traffic controller 4 to the on screen display (OSD)block 6. OSD block 6 decodes the on screen display data, for example, aprogram guide, constructs the on screen display information and assignsappropriate colors to each pixel using a color look-up table. Theon-screen display data is then mixed in mixer 9 with decoded video datafrom video decoder 7 for display.

In 4×3 display mode (i.e., where CRT 32 has a standard 4×3 aspectratio), the decoded video signal from video decoder 7 is passed thoughexpander 60 but is not expanded. However, when the output of videodecoder 7 is a 16×9 signal and CRT 32 has a 16×9 aspect ratio and 16×9display mode has been selected, expander 60 horizontally expands thevideo data provided by video decoder 7 to 16×9 format. In this case, thehorizontal pixel number will be enlarged four-thirds times. Furtherdetails of the 16×9 mode are described below.

In receiver/decoder mode, switch 10 is closed. Accordingly, mixer 9mixes the decoded video output from VDEC 7 and the on screen displaydata from OSD block 6 and passes the mixed signal to RGB converter 11.RGB converter 11 converts the digital bit stream to appropriate RGBsignals for CRT 32. The RGB signals are transmitted to digital-to-analogconverter 48 which converts the digital RGB signals to their analogequivalents. Switch 49 is closed and the analog RGB signals are passedto CRT 32 though mixer 47. Note that in receiver/decoder mode, switch 46will be open so no mixing occurs in mixer 47. The resulting signal isapplied to CRT 32 and video data is thereby displayed.

All of the above described blocks are under the control of CPU 15 whichprovides the appropriate control signals for the above operation. CPU 15may also handle user interface functions though a user interface block(not shown). This user interface block may be front panel controls or aninfra-red or other remote control. While in receiver/decoder mode, thetelevision circuits (described below) are placed in a low power or haltmode.

While in receiver/decoder mode, the output of video decoder 7 may alsobe sent to NTSC encoder 12 where it is converted to an analog NTSCsignal. This analog NTSC signal may be passed to an analog videocassette recorder to allow for recording of television programming. Itshould be noted that this embodiment of the present invention requiresonly one NTSC encoder whereas existing receiver/decoders require twoNTSC encoders, as shown in FIG. 1. By providing video signals directlyto CRT 32, the need for a second NTSC encoder is eliminated.

The integrated system shown in FIG. 2 also has a number of traditionaltelevision circuits. In television mode, i.e., when these televisioncircuits are in use, the receiver/decoder circuits described above willbe placed in a low power or halt mode by CPU 15. In this way, power isconserved.

In television mode, a signal from an antenna 112 or cable televisionsource 114 is first tuned to a desired channel at tuner 16 thenamplified in amplifier 17 and detected in detector 18. All of theseoperations are conventional and well known in the art Detector 18outputs a video signal and an audio signal. The audio signal is detectedby audio detector/amplifier 19 and passed to a speaker system thoughswitch 14.

The video signal from detector 18 is sampled by analog-to-digital (A/D)converter 21. The digital signal output from A/D converter 21 is passedto block 22 where the horizontal and vertical sync pulses are extractedand fed back to the sampling clock of A/D converter 21.

It should be noted that the television circuits also provide for thedetected video signal to be transmitted to an analog video cassetterecorder via an NTSC output. Because the signals are already in standardNTSC format, no encoder is required. In addition, analog signals from avideo cassette recorder can be passed to A/D converter 21 though an NTSCinput. In such a case, switch 20 would be oriented appropriately.

The digital signals from A/D converter 21 are passed to verticalblanking interval (VBI) decoder 23 which decodes any data contained inthe VBI (e.g., closed captioning data) of the NTSC signal and storesthis data in RAM 5 under the control of TC 4. The data stored in RAM 5is sent to OSD block 6 though TC 4 and decoded appropriately. Theluminance and chrominance outputs of OSD block 6 are converted to RGBformat in RGB converter 11 and then converted to an analog signal by D/Aconverter 48. The analog RGB signal is passed to mixer 47 though switch49 to allow the decoded VBI information to be displayed on CRT 32. Inaddition to VBI information, various other data can be displayed usingthe on screen display function while in the television mode. It shouldbe noted that in the television mode, switch 10 is open.

The digital NTSC signal from A/D converter 21 is also provided todigital process 40. Digital process 40 includes a luminance/chrominanceseparator and two non-interlace converters. FIG. 4 illustrates digitalprocess 40 in detail.

As shown in FIG. 4, digital process 40 consists of aluminance/chrominance separator 400 which separates the luminance (Y)and chrominance (C) information present in the NTSC signal. Chrominaceinformation is passed to non-interlace converter 401 while luminanceinformation is passed to non-interlace converter 402.

FIG. 5 illustrates luminace/chrominance separator 400 in detail. Thedigital NTSC signal from A/D converter 21 is filtered in band-passfilter 200 and transmitted to temporal filter 406 and vertical filter408. Temporal filter 406 consists of frame delay 202 and subtractor 203.Because the color sub-carrier in the digital NTSC signal is inverted ineach adjacent frame when the picture does not have any motion, temporalfilter 406 can extract the chrominance signal. Vertical filter 408 is athree tap high pass filter. It consists of line delays 204 and 205,mixer 206, and subtractor 207. Thus, luminance/chrominance separator 400is a typical two-dimensional luminance/chrominance separator as iscommon in the art.

Motion detector 201 of luminance/chrominance separator 400 detectsmotions in pictures. When the pictures have fewer motions, motiondetector 201 connects switch 208 to temporal filter 406. Otherwise,motion detector 201 connects switch 208 to vertical filter 408. Theoutput of switch 208 is the chrominance signal while the output ofsubtractor 209 is the luminance signal.

Although frame delay 202, line delay 204 and line delay 205 areillustrated as independent blocks in FIG. 5, those skilled in the artwill appreciate that these need not be separate components. In oneembodiment, the output signals from band-pass filter 200 are stored inRAM 5 under the control of traffic controller 4. To allow for thestorage, some areas of RAM 5 are assigned to frame memory and others areassigned to line memory. This is illustrated in FIG. 6. In this example,the area of RAM 5 between addresses A0 and A1 allows for the storage offrame delay 202. Storage for line delays 204 and 205 are assigned fromaddresses A1 and A2, respectfully. By utilizing RAM 5 in this manner,digital process 40 does not require a separate memory.

FIG. 7 illustrates non-interlace converters 401 and 402 of digitalprocess 40. Each of the non-interlace converters is identical. Blocks300, 301 and 302 are field delays. In order to interpolate betweenlines, the current line and the line two fields prior are added in adder304 and divided by 2. The output is passed to vertical high pass filter305. The output of delay 300 is passed to vertical low pass filter 306.Motion detector 303 detects motions in the pictures and adjusts theratio of mixing between the outputs of vertical high pass filter 305 andvertical low pass filter 306 in adder 307. When the pictures have fewermotions, the ratio of outputs from filter 305 to those from filter 306increases. In other cases, the ratio of outputs from filter 306 to thosefrom filter 305 increases. By adding the result to the original signalin adder 308, a non-interlaced signal output is obtained. It will beappreciated that, as was the case for line delays and frame delays 202,204 and 205, field delays 300, 301 and 302 need not be independentcomponents but may be areas assigned in RAM 5.

Returning to FIG. 2, the chrominance signal from digital process 40 isconverted to an analog signal by D/A converter 41. The analog signaloutput from D/A converter 41 undergoes chroma process 43 which is aconventional analog color signal decoder. Chroma process 43 outputs B-Yand R-Y signals to Matrix 45.

Luminance signal Y from digital process 40 is converted to an analogsignal by D/A 42. The output analog signal then undergoes luminanceprocess 44, which is a conventional analog luminance signalcontroller/amplifier. The output of luminance process 44 is alsoprovided to Matrix 45.

Matrix 45 converts the luminance and chrominance inputs described aboveto RGB signals and provides the RGB signals to mixer 47 though switch46. Mixer 47 mixes the RGB signals from Matrix 45 with any on screendisplay signals from D/A converter 48 and provides the mixed signaloutput to CRT 32. All of the above described blocks and processes areunder the control of CPU 15 which provides the appropriate controlsignals.

FIG. 3 illustrates a second embodiment of the integrated system. For theexample shown in FIG. 3, the NTSC decoding process for the televisioncircuitry is completely digitized. The same numerals are used in FIG. 3as in FIG. 2 for similar components.

There are two distinctions between the example shown in FIG. 2 and theexample shown in FIG. 3. First, for the example shown in FIG. 3, chromaprocess 25, luminance process 26 and Matrix 27 are all fully digitized.The digital processing mirrors that described above for the analog case,however, appropriate digital filters are used. These filters and digitalprocessing techniques are known in the television art. These blocks mayemploy RAM 5 as a common memory for the required digital signalprocessing operations. Second, the mixing operation provided by mixer 29is a digital mixing process. That is, the digital RGB signal from Matrix27 is mixed with a digital on screen display signal from OSD block 6before the mixed signal is finally converted to an analog output in D/Aconverter 31 for transmission to CRT 32. The output of Matrix 27 may bedigitally expanded in expander 61 if CRT 32 has a 16×9 aspect ratio.Otherwise, the signal is not expanded.

FIG. 8 show the case where the receiver/decoder decodes 16×9 squeezedvideo which is then displayed in 16×9 format. The use of 16×9 videosignals is becoming more and more common in the industry. However,because OSD data is typically not formatted for display on 16×9televisions, certain undesirable characteristics result. To illustrate,notice that for existing receiver/decoders, video decoder 7 decodes the16×9 squeezed picture. At this point, the video signals are "squeezed"as shown by illustration (ii). The on screen display data, in this casethe letter A, generated in OSD block 6 is not squeezed, as shown inillustration (i). These two signals are mixed in mixer 9 and NTSCencoded in NTSC encoder 100. The output of NTSC encoder 100 is shown inillustration (iii). It includes a squeezed video picture andnon-squeezed OSD information. A television NTSC decoder 500 decodes thissignal and expander 501 expands the signal to 16×9 size. The result isshown in illustration (iv). Not only is the squeezed video pictureexpanded (to yield a property formatted image), but the OSD data is alsoexpanded horizontally. This results in the OSD data being distorted onthe screen. This is an undesirable characteristic.

One solution to avoid this problem is to make the original OSD data"leaner" (i.e., squeeze the OSD signal) before it is mixed with thevideo signal in mixer 9. However, this solution would require thereceiver/decoder to generate two types of OSD data. This would benecessary because where the CRT 32 is operated in 4×3 mode, non-squeezedOSD data would be required. Alternatively, the receiver/decoder may havea software or hardware converter which compresses the OSD datahorizontally. Either way, additional memory will be required.

The present invention eliminates the problems described above. In thepresent invention, the receiver/decoder output is not NTSC encoded. Asdescribed above, the OSD data is mixed with already expanded video data.Therefore, OSD data need never be expanded prior to display, even if theCRT operates in a 16×9 mode. This eliminates the problem presented byexisting receiver decoders and it is a further advantage of the presentinvention.

In addition to the functions described above, a fully digitizedtelevision may have other functions such as noise reduction,picture-in-picture, etc. Where such functions are implemented, RAM 5 canbe used as a shared memory.

Thus, a television having an integrated receiver/decoder has beendescribed. Although features and examples of the present invention havebeen described with references to specific exemplary embodimentsthereof, those skilled in the art will appreciate that certainmodifications may be possible without departing from the broader spiritand scope of the invention which should be limited only by the claimswhich follow.

What is claimed is:
 1. A television, comprising:first circuitryconfigured to decode and display television signals having a firstsignal format; and second circuitry coupled to said first circuitryconfigured to decode and display television signals having a secondsignal format and further configured to encode said television signalsin said first signal format.
 2. A television as in claim 1 wherein saidfirst signal format is an NTSC format and said second signal format isan MPEG format.
 3. A television as in claim 2 wherein said firstcircuitry comprises:a first processor for separating luminance andchrominance information present in said NTSC format; and a secondprocessor coupled to said first processor for generating RGB signalsfrom said luminance and chrominance information.
 4. A television as inclaim 3 wherein said first processor includes a memory shared by saidsecond circuitry.
 5. A television as in claim 4 wherein said secondcircuitry comprises:a video decoder coupled to said memory, said videodecoder for decoding MPEG video signals present within said televisionsignals having said MPEG format; and an audio decoder coupled to saidmemory, said audio decoder for decoding MPEG audio signals presentwithin said television signals having said MPEG format.
 6. A televisionas in claim 5 wherein said television signals having said MPEG formatare encrypted prior to being transmitted and said second circuitryfurther comprises decryption means coupled to said memory for decryptingsaid encrypted television signals.
 7. A television as in claim 5 whereinsaid second circuitry comprises a digital satellite system integratedreceiver decoder.
 8. A method of mixing on-screen display data withvideo data for presentation on a television, the method comprising thesteps of:decoding said video data from a received television signal toproduce decoded video data; decoding said on-screen display data fromsaid received television signal to produce decoded on-screen displaydata; expanding said decoded video data to produce expanded aspect ratioformat video data; and mixing said expanded aspect ratio format videodata with said decoded on-screen display data to produce a mixed signal.9. The method of claim 8 further comprising the step of encoding saidmixed signal in a format for presentation on the television.
 10. Themethod of claim 9 wherein said format is an NTSC format.